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ICCD
2007
IEEE
205views Hardware» more  ICCD 2007»
14 years 3 months ago
Hardware libraries: An architecture for economic acceleration in soft multi-core environments
In single processor architectures, computationallyintensive functions are typically accelerated using hardware accelerators, which exploit the concurrency in the function code to ...
David Meisner, Sherief Reda
JNSM
2008
130views more  JNSM 2008»
13 years 6 months ago
Declarative Infrastructure Configuration Synthesis and Debugging
There is a large conceptual gap between end-to-end infrastructure requirements and detailed component configuration implementing those requirements. Today, this gap is manually br...
Sanjai Narain, Gary Levin, Sharad Malik, Vikram Ka...
SIGOPSE
2004
ACM
13 years 11 months ago
QoS for internet services: done right
In this paper we argue that the best approach to providing Quality of Service (QoS) guarantees to current Internet services is to use admission control and traffic shaping techni...
Josep M. Blanquer, Antoni Batchelli, Klaus E. Scha...
ISSS
2002
IEEE
103views Hardware» more  ISSS 2002»
13 years 11 months ago
A Symbolic Approach for the Combined Solution of Scheduling and Allocation
Scheduling is widely recognized as a very important step in highlevel synthesis. Nevertheless, it is usually done without taking into account the effects on the actual hardware im...
Luciano Lavagno, Mihai T. Lazarescu, Stefano Quer,...
EDO
2006
Springer
13 years 10 months ago
An extensible, lightweight architecture for adaptive J2EE applications
Server applications with adaptive behaviors can adapt their functionality in response to environmental changes, and significantly reduce the on-going costs of system deployment an...
Ian Gorton, Yan Liu, Nihar Trivedi