52 search results - page 1 / 11 » Cost and Benefit Models for Logic and Memory BIST |
42
Voted
DATE
2000
IEEE
15 years 2 months ago
2000
IEEE
DATE
2005
IEEE
15 years 3 months ago
2005
IEEE
A technique for evaluating noise figure suitable for BIST implementation is described. It is based on a low cost single-bit digitizer, which allows the simultaneous evaluation of ...
MTDT
2002
IEEE
15 years 2 months ago
2002
IEEE
The amount of memory being embedded on chip is growing rapidly. This strongly implies that memory Built-in-self-test (BIST) logic assumes utmost importance amongst all on chip sel...
ITC
2003
IEEE
15 years 3 months ago
2003
IEEE
1 This paper addresses the issue of testing and diagnosing a memory core embedded in a complex SOC. The proposed solution is based on a P1500-compliant wrapper that follows a progr...
ITC
2003
IEEE
15 years 3 months ago
2003
IEEE
ct This paper describes a general technique to test external memory/caches and memory interconnects using on-chip logic. Such a test methodology is expected to significantly reduc...