33 search results - page 4 / 7 » Cost-Effective Approach for Reducing Soft Error Failure Rate... |
FPGA
2005
ACM
13 years 11 months ago
2005
ACM
FPGA-based designs are more susceptible to single-event upsets (SEUs) compared to ASIC designs. Soft error rate (SER) estimation is a crucial step in the design of soft error tole...
VLSID
2006
IEEE
14 years 6 months ago
2006
IEEE
Radiation induced soft errors in combinational logic is expected to become as important as directly induced errors on state elements. Consequently, it has become important to deve...
ICCAD
2006
IEEE
14 years 3 months ago
2006
IEEE
Soft errors in logic are emerging as a significant reliability problem for VLSI designs. This paper presents novel circuit optimization techniques to mitigate soft error rates (SE...
ISQED
2009
IEEE
14 years 1 months ago
2009
IEEE
With technology scaling, the occurrence rate of not only single, but also multiple transients resulting from a single hit is increasing. In this work, we consider the effect of th...
IOLTS
2008
IEEE
14 years 19 days ago
2008
IEEE
Sets of Pairs of Functions to be Distinguished (SPFD) is a functional flexibility representation method that was recently introduced in the logic synthesis domain, and promises s...