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» Cost-driven 3D integration with interconnect layers
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3DIC
2009
IEEE
263views Hardware» more  3DIC 2009»
15 years 27 days ago
3D optical networks-on-chip (NoC) for multiprocessor systems-on-chip (MPSoC)
Abstract— Networks-on-chip (NoC) is emerging as a key onchip communication architecture for multiprocessor systemson-chip (MPSoC). In traditional electronic NoCs, high bandwidth ...
Yaoyao Ye, Lian Duan, Jiang Xu, Jin Ouyang, Mo Kwa...
ISVLSI
2003
IEEE
91views VLSI» more  ISVLSI 2003»
15 years 2 months ago
Three-Dimensional Integrated Circuits: Performance, Design Methodology, and CAD Tools
Three-dimensional integration technologies have been proposed in order to mitigate design challenges posed by deep-submicron interconnect. By providing multiple layers of active d...
Shamik Das, Anantha Chandrakasan, Rafael Reif
ISCA
2008
IEEE
188views Hardware» more  ISCA 2008»
15 years 4 months ago
MIRA: A Multi-layered On-Chip Interconnect Router Architecture
Recently, Network-on-Chip (NoC) architectures have gained popularity to address the interconnect delay problem for designing CMP / multi-core / SoC systems in deep sub-micron tech...
Dongkook Park, Soumya Eachempati, Reetuparna Das, ...
ICCD
2005
IEEE
101views Hardware» more  ICCD 2005»
15 years 6 months ago
Three-Dimensional Cache Design Exploration Using 3DCacti
As technology scales, interconnects dominate the performance and power behavior of deep submicron designs. Three-dimensional integrated circuits (3D ICs) have been proposed as a w...
Yuh-Fang Tsai, Yuan Xie, Narayanan Vijaykrishnan, ...
DAC
2006
ACM
15 years 3 months ago
A high density, carbon nanotube capacitor for decoupling applications
We present a novel application for carbon nanotube devices, implementing a high density 3-D capacitor, which can be useful for decoupling applications to reduce supply voltage var...
Mark M. Budnik, Arijit Raychowdhury, Aditya Bansal...