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ISCA
2000
IEEE
111views Hardware» more  ISCA 2000»
15 years 2 months ago
Understanding the backward slices of performance degrading instructions
For many applications, branch mispredictions and cache misses limit a processor’s performance to a level well below its peak instruction throughput. A small fraction of static i...
Craig B. Zilles, Gurindar S. Sohi
ICS
1999
Tsinghua U.
15 years 2 months ago
Clustered speculative multithreaded processors
In this paper we present a processor microarchitecture that can simultaneously execute multiple threads and has a clustered design for scalability purposes. A main feature of the ...
Pedro Marcuello, Antonio González
DEBS
2008
ACM
14 years 11 months ago
Speculative out-of-order event processing with software transaction memory
In event stream applications, events flow through a network of components that perform various types of operations, e.g., filtering, aggregation, transformation. When the operatio...
Andrey Brito, Christof Fetzer, Heiko Sturzrehm, Pa...
NIPS
2008
14 years 11 months ago
On Computational Power and the Order-Chaos Phase Transition in Reservoir Computing
Randomly connected recurrent neural circuits have proven to be very powerful models for online computations when a trained memoryless readout function is appended. Such Reservoir ...
Benjamin Schrauwen, Lars Buesing, Robert A. Legens...
NECO
2010
147views more  NECO 2010»
14 years 8 months ago
Connectivity, Dynamics, and Memory in Reservoir Computing with Binary and Analog Neurons
Abstract: Reservoir Computing (RC) systems are powerful models for online computations on input sequences. They consist of a memoryless readout neuron which is trained on top of a ...
Lars Büsing, Benjamin Schrauwen, Robert A. Le...