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» Counting Models Using Connected Components
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FDL
2004
IEEE
15 years 1 months ago
A Formal Verification Approach for IP-based Designs
This paper proposes a formal verification methodology which is smoothly integrated with component-based system-level design, using a divide and conquer approach. The methodology a...
Daniel Karlsson, Petru Eles, Zebo Peng
CF
2007
ACM
15 years 1 months ago
Reconfigurable hybrid interconnection for static and dynamic scientific applications
As we enter the era of petascale computing, system architects must plan for machines composed of tens or even hundreds of thousands of processors. Although fully connected network...
Shoaib Kamil, Ali Pinar, Daniel Gunter, Michael Li...
EDBT
2012
ACM
228views Database» more  EDBT 2012»
13 years 5 days ago
Finding maximal k-edge-connected subgraphs from a large graph
In this paper, we study how to find maximal k-edge-connected subgraphs from a large graph. k-edge-connected subgraphs can be used to capture closely related vertices, and findin...
Rui Zhou, Chengfei Liu, Jeffrey Xu Yu, Weifa Liang...
ESWA
2008
166views more  ESWA 2008»
14 years 9 months ago
Modular design to support green life-cycle engineering
The severe competition in the market has driven enterprises to produce a wider variety of products to meet consumers' needs. However, frequent variation of product specificat...
Hwai-En Tseng, Chien-Chen Chang, Jia-Diann Li
HPCA
2009
IEEE
15 years 10 months ago
Express Cube Topologies for on-Chip Interconnects
Driven by continuing scaling of Moore's law, chip multiprocessors and systems-on-a-chip are expected to grow the core count from dozens today to hundreds in the near future. ...
Boris Grot, Joel Hestness, Stephen W. Keckler, Onu...