76 search results - page 13 / 16 » Counting Solutions of Knapsack Constraints |
DAC
2005
ACM
15 years 10 months ago
2005
ACM
In this paper we present a system level technique for mapping large, multiple-IP-block designs to channel-width constrained FPGAs. Most FPGA clustering tools [2, 3, 11] aim to red...
MICRO
2006
IEEE
15 years 3 months ago
2006
IEEE
VLIW and EDGE (Explicit Data Graph Execution) architectures rely on compilers to form high-quality hyperblocks for good performance. These compilers typically perform hyperblock f...
DISOPT
2007
14 years 9 months ago
2007
The class Max (r, 2)-CSP (or simply Max 2-CSP) consists of constraint satisfaction problems with at most two r-valued variables per clause. For instances with n variables and m bin...
ICDE
2009
IEEE
15 years 4 months ago
2009
IEEE
— To explore the benefit of advertising instant and location-aware commercials that can not be effectively promoted by traditional medium like TV program and Internet, we propos...
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Voted
DATE
2009
IEEE
15 years 4 months ago
2009
IEEE
—The sustained push for performance, transistor count, and instruction level parallelism has reached a point where chip level power density issues are at the forefront of design ...