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» Counting in the Presence of Memory Faults
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SPDP
1991
IEEE
15 years 3 months ago
Fault-tolerant meshes with minimal numbers of spares
This paper presents several techniques for adding fault-tolerance to distributed memory parallel computers. More formally, given a target graph with n nodes, we create a fault-tol...
Jehoshua Bruck, Robert Cypher, Ching-Tien Ho
CORR
2009
Springer
74views Education» more  CORR 2009»
14 years 9 months ago
Parallelizing Deadlock Resolution in Symbolic Synthesis of Distributed Programs
Previous work has shown that there are two major complexity barriers in the synthesis of fault-tolerant distributed programs, namely generation of fault-span, the set of states re...
Fuad Abujarad, Borzoo Bonakdarpour, Sandeep S. Kul...
CONCURRENCY
2010
110views more  CONCURRENCY 2010»
14 years 11 months ago
Redesigning the message logging model for high performance
Over the past decade the number of processors in the high performance facilities went up to hundreds of thousands. As a direct consequence, while the computational power follow th...
Aurelien Bouteiller, George Bosilca, Jack Dongarra
ISCA
2005
IEEE
119views Hardware» more  ISCA 2005»
15 years 5 months ago
Rescue: A Microarchitecture for Testability and Defect Tolerance
Scaling feature size improves processor performance but increases each device’s susceptibility to defects (i.e., hard errors). As a result, fabrication technology must improve s...
Ethan Schuchman, T. N. Vijaykumar
91
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EUROCRYPT
2006
Springer
15 years 3 months ago
Private Circuits II: Keeping Secrets in Tamperable Circuits
Abstract. Motivated by the problem of protecting cryptographic hardware, we continue the investigation of private circuits initiated in [16]. In this work, our aim is to construct ...
Yuval Ishai, Manoj Prabhakaran, Amit Sahai, David ...