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» Coverage Metrics for Temporal Logic Model Checking
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VTS
2002
IEEE
120views Hardware» more  VTS 2002»
15 years 2 months ago
Software-Based Weighted Random Testing for IP Cores in Bus-Based Programmable SoCs
We present a software-based weighted random pattern scheme for testing delay faults in IP cores of programmable SoCs. We describe a method for determining static and transition pr...
Madhu K. Iyer, Kwang-Ting Cheng
81
Voted
DAC
2007
ACM
15 years 1 months ago
A Framework for the Validation of Processor Architecture Compliance
We present a framework for validating the compliance of a design with a given architecture. Our approach is centered on the concept of misinterpretations. These include missing be...
Allon Adir, Sigal Asaf, Laurent Fournier, Itai Jae...
POPL
2003
ACM
15 years 9 months ago
From symptom to cause: localizing errors in counterexample traces
There is significant room for improving users' experiences with model checking tools. An error trace produced by a model checker can be lengthy and is indicative of a symptom...
Thomas Ball, Mayur Naik, Sriram K. Rajamani
AOSD
2009
ACM
14 years 12 months ago
Modular verification of dynamically adaptive systems
Cyber-physical systems increasingly rely on dynamically adaptive programs to respond to changes in their physical environment; examples include ecosystem monitoring and disaster r...
Ji Zhang, Heather Goldsby, Betty H. C. Cheng
FASE
2004
Springer
15 years 1 months ago
Specification and Analysis of Real-Time Systems Using Real-Time Maude
Real-Time Maude is a language and tool supporting the formal specification and analysis of real-time and hybrid systems. The specification formalism is based on rewriting logic, em...
Peter Csaba Ölveczky, José Meseguer