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» Criteria for the verification of feature models
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AOSD
2009
ACM
15 years 4 months ago
Modelling hardware verification concerns specified in the e language: an experience report
e is an aspect-oriented hardware verification language that is widely used to verify the design of electronic circuits through the development and execution of testbenches. In rec...
Darren Galpin, Cormac Driver, Siobhán Clark...
DFG
2004
Springer
15 years 1 months ago
Modeling and Formal Verification of Production Automation Systems
This paper presents the real-time model checker RAVEN and related theoretical background. RAVEN augments the efficiency of traditional symbolic model checking with possibilities to...
Jürgen Ruf, Roland J. Weiss, Thomas Kropf, Wo...
DAC
1999
ACM
15 years 2 months ago
Cycle and Phase Accurate DSP Modeling and Integration for HW/SW Co-Verification
We present our practical experience in the modeling and integration of cycle/phase-accurate instruction set architecture (ISA) models of digital signal processors (DSPs) with othe...
Lisa M. Guerra, Joachim Fitzner, Dipankar Talukdar...
EURODAC
1994
IEEE
211views VHDL» more  EURODAC 1994»
15 years 2 months ago
Advanced simulation and modeling techniques for hardware quality verification of digital systems
synchronisation also play a fundamental role in overall system robustness. ElectroMagnetic Compatibility (EMC) and ElectroMagnetic Interference (EMI) issues also have to be conside...
S. Forno, Stephen Rochel
CVPR
2006
IEEE
15 years 1 months ago
Multiple Face Model of Hybrid Fourier Feature for Large Face Image Set
The face recognition system based on the only single classifier considering the restricted information can not guarantee the generality and superiority of performances in a real s...
Wonjun Hwang, Gyu-tae Park, Jong Ha Lee, Seok-Cheo...