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» Crosstalk analysis in nanometer technologies
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ASPDAC
2008
ACM
104views Hardware» more  ASPDAC 2008»
14 years 11 months ago
Pessimism reduction in coupling-aware static timing analysis using timing and logic filtering
With continued scaling of technology into nanometer regimes, the impact of coupling induced delay variations is significant. While several coupling-aware static timers have been pr...
Debasish Das, Kip Killpack, Chandramouli V. Kashya...
DAC
2003
ACM
15 years 10 months ago
A survey of techniques for energy efficient on-chip communication
Interconnects have been shown to be a dominant source of energy consumption in modern day System-on-Chip (SoC) designs. With a large (and growing) number of electronic systems bei...
Vijay Raghunathan, Mani B. Srivastava, Rajesh K. G...
DAC
2007
ACM
15 years 10 months ago
The Case for Low-Power Photonic Networks on Chip
Packet-switched networks on chip (NoC) have been advocated as a natural communication mechanism among the processing cores in future chip multiprocessors (CMP). However, electroni...
Assaf Shacham, Keren Bergman, Luca P. Carloni
ICCAD
2007
IEEE
132views Hardware» more  ICCAD 2007»
15 years 6 months ago
Principle Hessian direction based parameter reduction with process variation
— As CMOS technology enters the nanometer regime, the increasing process variation is bringing manifest impact on circuit performance. In this paper, we propose a Principle Hessi...
Alexander V. Mitev, Michael Marefat, Dongsheng Ma,...
DATE
2007
IEEE
130views Hardware» more  DATE 2007»
15 years 3 months ago
A novel criticality computation method in statistical timing analysis
Abstract— The impact of process variations increases as technology scales to nanometer region. Under large process variations, the path and arc/node criticality [18] provide effe...
Feng Wang 0004, Yuan Xie, Hai Ju