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GLVLSI
2007
IEEE
107views VLSI» more  GLVLSI 2007»
15 years 10 months ago
Side-channel resistant system-level design flow for public-key cryptography
In this paper, we propose a new design methodology to assess the risk for side-channel attacks, more specifically timing analysis and simple power analysis, at an early design st...
Kazuo Sakiyama, Elke De Mulder, Bart Preneel, Ingr...
DAC
2007
ACM
15 years 7 months ago
Trusted Design in FPGAs
Using FPGAs, a designer can separate the design process from the manufacturing flow. Therefore, the owner of a sensitive design need not expose the design to possible theft and ta...
Steven Trimberger
ISCAS
2008
IEEE
185views Hardware» more  ISCAS 2008»
15 years 10 months ago
A full-custom design of AES SubByte module with signal independent power consumption
—A full-custom design of AES SubByte module based on Sense Amplifier Based Logic is proposed in this paper. Power consumption of this design is independent of both value and sequ...
Liang Li, Jun Han, Xiaoyang Zeng, Jia Zhao
GLVLSI
2007
IEEE
162views VLSI» more  GLVLSI 2007»
15 years 10 months ago
Design of an UHF RFID transponder for secure authentication
RFID technology increases rapidly its applicability in new areas of interest without guaranteeing security and privacy issues. This paper presents a new architecture of an RFID tr...
Paolo Bernardi, Filippo Gandino, Bartolomeo Montru...
IJNSEC
2008
113views more  IJNSEC 2008»
15 years 3 months ago
Multi-Designated Verifiers Signatures Revisited
Multi-Designated Verifier Signatures (MDVS) are privacy-oriented signatures that can only be verified by a set of users specified by the signer. We propose two new generic constru...
Sherman S. M. Chow