2896 search results - page 460 / 580 » Curricula Modeling and Checking |
152
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ATVA
2007
Springer
15 years 10 months ago
2007
Springer
Abstract. Symbolic Trajectory Evaluation (STE) is a powerful technique for hardware model checking. It is based on a 3-valued symbolic simulation, using 0,1 and X n"), where t...
193
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ATVA
2006
Springer
15 years 9 months ago
2006
Springer
Abstract. Model-checking alternating-time properties has recently attracted much interest in the verification of distributed protocols. While checking the validity of a specificati...
159
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AUSDM
2006
Springer
15 years 9 months ago
2006
Springer
Predictive accuracy claims should give explicit descriptions of the steps followed, with access to the code used. This allows referees and readers to check for common traps, and t...
136
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CHARME
2003
Springer
15 years 9 months ago
2003
Springer
Industrial verification teams are actively developing suitable event sequence languages for hardware verification. Such languages must be expressive, designer friendly, and hardwar...
152
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ASIACRYPT
2008
Springer
15 years 8 months ago
2008
Springer
In a proof-of-retrievability system, a data storage center must prove to a verifier that he is actually storing all of a client's data. The central challenge is to build syst...