58 search results - page 7 / 12 » Customizable Fault Tolerant Caches for Embedded Processors |
DATE
2007
IEEE
15 years 6 months ago
2007
IEEE
Device scaling in new and future technologies brings along severe increase in the soft error rate of circuits, for combinational and sequential logic. Although potential solutions...
100
Voted
ISCA
2009
IEEE
15 years 6 months ago
2009
IEEE
The incidence of hard errors in CPUs is a challenge for future multicore designs due to increasing total core area. Even if the location and nature of hard errors are known a prio...
ET
2008
14 years 11 months ago
2008
Processor cores embedded in systems-on-a-chip (SoCs) are often deployed in critical computations, and when affected by faults they may produce dramatic effects. When hardware harde...
DAC
2009
ACM
16 years 19 days ago
2009
ACM
Post-silicon processor debugging is frequently carried out in a loop consisting of several iterations of the following two key steps: (i) processor execution for some duration, fo...
110
click to vote
ISPA
2007
Springer
15 years 5 months ago
2007
Springer
The number of processors embedded in high performance computing platforms is growing daily to solve larger and more complex problems. The logical network topologies must also suppo...