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JCIT
2007
63views more  JCIT 2007»
14 years 9 months ago
Optimizing Reaching Definitions Overhead in Queue Processors
Queue computers are a viable option for embedded systems design. Queue computers feature a dense instruction set, high parallelism, low hardware complexity. In this paper we propo...
Yuki Nakanishi, Arquimedes Canedo, Ben A. Abderaze...
CODES
2006
IEEE
15 years 1 months ago
Application specific forwarding network and instruction encoding for multi-pipe ASIPs
Small area and code size are two critical design issues in most of embedded system designs. In this paper, we tackle these issues by customizing forwarding networks and instructio...
Swarnalatha Radhakrishnan, Hui Guo, Sri Parameswar...
ESTIMEDIA
2005
Springer
15 years 3 months ago
Custom Processor Design Using NISC: A Case-Study on DCT algorithm
Designing Application-Specific Instruction-set Processors (ASIPs) usually requires designing a custom datapath, and modifying instruction-set, instruction decoder, and compiler. A...
Bita Gorjiara, Daniel D. Gajski
ISLPED
2000
ACM
68views Hardware» more  ISLPED 2000»
15 years 2 months ago
Speeding up power estimation of embedded software
Power is increasingly becoming a design constraint for embedded systems. A processor is responsible for energy consumption on account of the software component of the embedded sys...
Akshaye Sama, J. F. M. Theeuwen, M. Balakrishnan
ASAP
2008
IEEE
105views Hardware» more  ASAP 2008»
14 years 11 months ago
Fast custom instruction identification by convex subgraph enumeration
Automatic generation of custom instruction processors from high-level application descriptions enables fast design space exploration, while offering very favorable performance and...
Kubilay Atasu, Oskar Mencer, Wayne Luk, Can C. &Ou...