209 search results - page 17 / 42 » Customized Instruction-Sets for Embedded Processors |
DAC
2001
ACM
15 years 10 months ago
2001
ACM
We present a methodology for microarchitectural customization of embedded processors by exploiting application information, thus attaining the twin benefits of processor standardi...
86
Voted
DAC
2006
ACM
15 years 10 months ago
2006
ACM
In this paper, we present a methodology for low-cost and rapid context switch for multithreaded embedded processors with realtime guarantees. Context-switch, which involves saving...
ISSS
1995
IEEE
15 years 1 months ago
1995
IEEE
This paper examines the problem of code-generation for expression trees on non-homogeneous register set architectures. It proposes and proves the optimality of an O(n) algorithm f...
ICCAD
2005
IEEE
15 years 6 months ago
2005
IEEE
—Existing ASIPs (application-specific instruction-set processors) and compiler-based co-processor synthesis approaches meet the increasing performance requirements of embedded ap...
DATE
2007
IEEE
15 years 4 months ago
2007
IEEE
Modern Application Specific Instruction Set Processors (ASIPs) have customizable caches, where the size, associativity and line size can all be customized to suit a particular ap...