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» Customized Instruction-Sets for Embedded Processors
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73
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ATS
2003
IEEE
131views Hardware» more  ATS 2003»
15 years 3 months ago
Software-Based Delay Fault Testing of Processor Cores
Software-based self-testing is a promising approach for the testing of processor cores which are embedded inside a System-on-a-Chip (SoC), as it can apply test vectors in function...
Virendra Singh, Michiko Inoue, Kewal K. Saluja, Hi...
PATMOS
2004
Springer
15 years 3 months ago
Application Analysis with Integrated Identification of Complex Instructions for Configurable Processors
Abstract. An extensible and configurable processor is a programmable platform offering the possibility to customize the instruction set and/or underlying microarchitecture. Efficie...
Nikolaos Kavvadias, Spiridon Nikolaidis
88
Voted
FPL
2010
Springer
267views Hardware» more  FPL 2010»
14 years 7 months ago
A Comparison of Hardware Acceleration Interfaces in a Customizable Soft Core Processor
Due to the continuously decreasing cost of FPGAs, they have become a valid implementation platform for SOCs. Typically, a soft core processor implementation is used to execute the ...
Gerald Hempel, Christian Hochberger, Andreas Koch
MICRO
2002
IEEE
173views Hardware» more  MICRO 2002»
15 years 2 months ago
Vector vs. superscalar and VLIW architectures for embedded multimedia benchmarks
Multimedia processing on embedded devices requires an architecture that leads to high performance, low power consumption, reduced design complexity, and small code size. In this p...
Christoforos E. Kozyrakis, David A. Patterson
62
Voted
ISCAS
2008
IEEE
133views Hardware» more  ISCAS 2008»
15 years 4 months ago
A hybrid self-testing methodology of processor cores
—Software-based self-test (SBST) is a promising new technology for at-speed testing of embedded processors in SoC systems. This paper introduces an effective and efficient new ho...
Tai-Hua Lu, Chung-Ho Chen, Kuen-Jong Lee