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DAC
2009
ACM
15 years 4 months ago
Clock skew optimization via wiresizing for timing sign-off covering all process corners
Manufacturing process variability impacts the performance of synchronous logic circuits by means of its effect on both clock network and functional block delays. Typically, varia...
Sari Onaissi, Khaled R. Heloue, Farid N. Najm
ECRTS
2003
IEEE
15 years 3 months ago
Using Supertasks to Improve Processor Utilization in Multiprocessor Real-Time Systems
We revisit the problem of supertasking in Pfair-scheduled multiprocessor systems. In this approach, a set of tasks, called component tasks, is assigned to a server task, called a ...
Philip Holman, James H. Anderson
ISQED
2008
IEEE
153views Hardware» more  ISQED 2008»
15 years 4 months ago
Accelerating Clock Mesh Simulation Using Matrix-Level Macromodels and Dynamic Time Step Rounding
Clock meshes have found increasingly wide applications in today’s high-performance IC designs. The inherent routing redundancies associated with clock meshes lead to improved cl...
Xiaoji Ye, Min Zhao, Rajendran Panda, Peng Li, Jia...
IJVR
2006
199views more  IJVR 2006»
14 years 10 months ago
Interactive Virtual Humans in Real-Time Virtual Environments
In this paper, we will present an overview of existing research in the vast area of IVH systems. We will also present our ongoing work on improving the expressive capabilities of I...
Nadia Magnenat-Thalmann, Arjan Egges
DATE
2005
IEEE
154views Hardware» more  DATE 2005»
15 years 3 months ago
Secure Embedded Processing through Hardware-Assisted Run-Time Monitoring
— Security is emerging as an important concern in embedded system design. The security of embedded systems is often compromised due to vulnerabilities in “trusted” software t...
Divya Arora, Srivaths Ravi, Anand Raghunathan, Nir...