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ISCA
2007
IEEE
192views Hardware» more  ISCA 2007»
15 years 4 months ago
Analysis of redundancy and application balance in the SPEC CPU2006 benchmark suite
The recently released SPEC CPU2006 benchmark suite is expected to be used by computer designers and computer architecture researchers for pre-silicon early design analysis. Partia...
Aashish Phansalkar, Ajay Joshi, Lizy Kurian John
AINA
2006
IEEE
15 years 4 months ago
Accelerating the HMMER Sequence Analysis Suite Using Conventional Processors
Due to the ever-increasing size of sequence databases it has become clear that faster techniques must be employed to effectively perform biological sequence analysis in a reasonab...
John Paul Walters, Bashar Qudah, Vipin Chaudhary
MMB
2004
Springer
175views Communications» more  MMB 2004»
15 years 3 months ago
Sensitivity Analysis for MAP/MAP/1 Queues
A sensitivity analysis of a single-server, infinite-buffer queue with correlated arrivals and correlated service times is performed. We study and compare the isolated impact of (...
Armin Heindl
ISSRE
2010
IEEE
14 years 8 months ago
A Large-Scale Industrial Case Study on Architecture-Based Software Reliability Analysis
—Architecture-based software reliability analysis methods shall help software architects to identify critical software components and to quantify their influence on the system r...
Heiko Koziolek, Bastian Schlich, Carlos G. Bilich
SIGMETRICS
1999
ACM
130views Hardware» more  SIGMETRICS 1999»
15 years 2 months ago
Address Trace Compression Through Loop Detection and Reduction
ded Abstract This paper introduces a new technique for compressing memory address traces. The technique relies on the simple observation that most programs spend their time execut...
E. N. Elnozahy