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ICS
1999
Tsinghua U.
15 years 4 months ago
An experimental evaluation of tiling and shackling for memory hierarchy management
On modern computers, the performance of programs is often limited by memory latency rather than by processor cycle time. To reduce the impact of memory latency, the restructuring ...
Induprakas Kodukula, Keshav Pingali, Robert Cox, D...
ISCA
1998
IEEE
139views Hardware» more  ISCA 1998»
15 years 4 months ago
Simultaneous Multithreading: Maximizing On-Chip Parallelism
This paper examines simultaneous multithreading, a technique permitting several independent threads to issue instructions to a superscalar's multiple functional units in a si...
Dean M. Tullsen, Susan J. Eggers, Henry M. Levy
100
Voted
VLDB
1997
ACM
109views Database» more  VLDB 1997»
15 years 4 months ago
Logical and Physical Versioning in Main Memory Databases
We present a design for multi-version concurrency control and recovery in a main memory database, and describe logical and physical versioning schemes that allow read-only transac...
Rajeev Rastogi, S. Seshadri, Philip Bohannon, Denn...
77
Voted
ASYNC
2004
IEEE
107views Hardware» more  ASYNC 2004»
15 years 4 months ago
Analog Micropipeline Rings for High Precision Timing
I use asynchronous FIFO stages that are connected in rings to generate and deliver highly precise timing signals. I introduce a Micropipeline FIFO control stage that oscillates at...
Scott Fairbanks, Simon W. Moore
ARCS
2006
Springer
15 years 4 months ago
Estimating Energy Consumption for an MPSoC Architectural Exploration
Early energy estimation is increasingly important in MultiProcessor System-On-Chip (MPSoC) design. Applying traditional approaches, which consist in delaying the estimation until t...
Rabie Ben Atitallah, Smaïl Niar, Alain Greine...