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VLSID
2009
IEEE
155views VLSI» more  VLSID 2009»
16 years 1 months ago
Unified Challenges in Nano-CMOS High-Level Synthesis
: The challenges in nano-CMOS circuit design include the following: variability, leakage, power, thermals, reliability, and yield. This talk will focus on interdependent considerat...
Saraju P. Mohanty
VLSID
2008
IEEE
150views VLSI» more  VLSID 2008»
16 years 1 months ago
PTSMT: A Tool for Cross-Level Power, Performance, and Thermal Exploration of SMT Processors
Simultaneous Multi-Threading (SMT) processors are becoming popular because they exploit both instruction-level and threadlevel parallelism by issuing instructions from different t...
Deepa Kannan, Aseem Gupta, Aviral Shrivastava, Nik...
VLSID
2008
IEEE
138views VLSI» more  VLSID 2008»
16 years 1 months ago
Memory Architecture Exploration Framework for Cache Based Embedded SOC
Today's feature-rich multimedia products require embedded system solution with complex System-on-Chip (SoC) to meet market expectations of high performance at a low cost and l...
T. S. Rajesh Kumar, C. P. Ravikumar, R. Govindaraj...
STOC
2003
ACM
188views Algorithms» more  STOC 2003»
16 years 1 months ago
Almost random graphs with simple hash functions
We describe a simple randomized construction for generating pairs of hash functions h1, h2 from a universe U to ranges V = [m] = {0, 1, . . . , m - 1} and W = [m] so that for ever...
Martin Dietzfelbinger, Philipp Woelfel
EWSN
2010
Springer
15 years 10 months ago
Phoenix: An Epidemic Approach to Time Reconstruction
Abstract. Harsh deployment environments and uncertain run-time conditions create numerous challenges for postmortem time reconstruction methods. For example, motes often reboot and...
Jayant Gupchup, Douglas Carlson, Razvan Musaloiu-E...