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112
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IPPS
2009
IEEE
15 years 7 months ago
Power-aware dynamic task scheduling for heterogeneous accelerated clusters
Recent accelerators such as GPUs achieve better cost-performance and watt-performance ratio, while the range of their application is more limited than general CPUs. Thus heterogen...
Tomoaki Hamano, Toshio Endo, Satoshi Matsuoka
92
Voted
ICCD
2008
IEEE
142views Hardware» more  ICCD 2008»
15 years 9 months ago
Making register file resistant to power analysis attacks
— Power analysis attacks are a type of side-channel attacks that exploits the power consumption of computing devices to retrieve secret information. They are very effective in br...
Shuo Wang, Fan Zhang, Jianwei Dai, Lei Wang, Zhiji...
100
Voted
CODES
2005
IEEE
15 years 6 months ago
Power-smart system-on-chip architecture for embedded cryptosystems
In embedded cryptosystems, sensitive information can leak via timing, power, and electromagnetic channels. We introduce a novel power-smart system-on-chip architecture that provid...
Radu Muresan, Haleh Vahedi, Y. Zhanrong, Stefano G...
123
Voted
IESS
2007
Springer
165views Hardware» more  IESS 2007»
15 years 6 months ago
Data Reuse Driven Memory and Network-On-Chip Co-Synthesis
NoCs present a possible communication infrastructure solution to deal with increased design complexity and shrinking time-to-market. The communication infrastructure is a signific...
Ilya Issenin, Nikil Dutt
SOSP
2005
ACM
15 years 9 months ago
Hibernator: helping disk arrays sleep through the winter
Energy consumption has become an important issue in high-end data centers, and disk arrays are one of the largest energy consumers within them. Although several attempts have been...
Qingbo Zhu, Zhifeng Chen, Lin Tan, Yuanyuan Zhou, ...