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ISCAS
2011
IEEE
261views Hardware» more  ISCAS 2011»
14 years 5 months ago
Optimization of area in digit-serial Multiple Constant Multiplications at gate-level
— The last two decades have seen many efficient algorithms and architectures for the design of low-complexity bit-parallel Multiple Constant Multiplications (MCM) operation, tha...
Levent Aksoy, Cristiano Lazzari, Eduardo Costa, Pa...
HYBRID
2011
Springer
14 years 1 months ago
Resource constrained LQR control under fast sampling
We investigate a state feedback Linear Quadratic Regulation problem with a constraint on the number of actuation signals that can be updated simultaneously. Such a constraint aris...
Jerome Le Ny, Eric Feron, George J. Pappas
FCCM
2006
IEEE
195views VLSI» more  FCCM 2006»
15 years 7 months ago
A Parallel Hardware Architecture for fast Gaussian Elimination over GF(2)
This paper presents a hardware-optimized variant of the well-known Gaussian elimination over GF(2) and its highly efficient implementation. The proposed hardware architecture, we...
Andrey Bogdanov, M. C. Mertens
ERSA
2006
129views Hardware» more  ERSA 2006»
15 years 3 months ago
Group-Alignment based Accurate Floating-Point Summation on FPGAs
Floating-point summation is one of the most important operations in scientific/numerical computing applications and also a basic subroutine (SUM) in BLAS (Basic Linear Algebra Sub...
Chuan He, Guan Qin, Mi Lu, Wei Zhao
BMCBI
2007
197views more  BMCBI 2007»
15 years 1 months ago
Boolean networks using the chi-square test for inferring large-scale gene regulatory networks
Background: Boolean network (BN) modeling is a commonly used method for constructing gene regulatory networks from time series microarray data. However, its major drawback is that...
Haseong Kim, Jae K. Lee, Taesung Park