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100
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ISCAS
2005
IEEE
132views Hardware» more  ISCAS 2005»
15 years 9 months ago
A high performance distributed-parallel-processor architecture for 3D IIR digital filters
—Real-time spatio-temporal VLSI 3D IIR digital filters may be used for imaging or beamforming applications employing 3D input signals from synchronously-sampled multi-sensor arra...
Arjuna Madanayake, Leonard T. Bruton
147
Voted
CVPR
2003
IEEE
16 years 5 months ago
Recognising and Monitoring High-Level Behaviours in Complex Spatial Environments
The recognition of activities from sensory data is important in advanced surveillance systems to enable prediction of high-level goals and intentions of the target under surveilla...
Nam Thanh Nguyen, Hung Hai Bui, Svetha Venkatesh, ...
150
Voted
IPPS
2005
IEEE
15 years 9 months ago
Automated Analysis of Memory Access Behavior
Abstract— We developed an automated environment to measure the memory access behavior of applications on high performance clusters. Code optimization for processor caches is cruc...
Michael Gerndt, Tianchao Li
133
Voted
HPCN
2000
Springer
15 years 7 months ago
A Java-Based Parallel Programming Support Environment
The Java programming language and environment is stimulating new research activities in many areas of computing, not the least of which is parallel computing. Parallel techniques ...
Kenneth A. Hawick, Heath A. James
121
Voted
PVM
2004
Springer
15 years 9 months ago
TEG: A High-Performance, Scalable, Multi-network Point-to-Point Communications Methodology
Abstract. TEG is a new component-based methodology for point-to-point messaging. Developed as part of the Open MPI project, TEG provides a configurable fault-tolerant capability f...
Timothy S. Woodall, Richard L. Graham, Ralph H. Ca...