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INFOCOM
2012
IEEE
13 years 6 months ago
Fair background data transfers of minimal delay impact
—In this paper we present a methodology for the design of congestion control protocols for background data transfers that have a minimal delay impact on short TCP transfers and c...
Costas Courcoubetis, Antonis Dimakis
ICS
2009
Tsinghua U.
15 years 10 months ago
Parametric multi-level tiling of imperfectly nested loops
Tiling is a crucial loop transformation for generating high performance code on modern architectures. Efficient generation of multilevel tiled code is essential for maximizing da...
Albert Hartono, Muthu Manikandan Baskaran, C&eacut...
140
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PPAM
2007
Springer
15 years 10 months ago
Parallel Tiled QR Factorization for Multicore Architectures
As multicore systems continue to gain ground in the High Performance Computing world, linear algebra algorithms have to be reformulated or new algorithms have to be developed in or...
Alfredo Buttari, Julien Langou, Jakub Kurzak, Jack...
EUROPAR
2009
Springer
15 years 8 months ago
Accelerating S3D: A GPGPU Case Study
The graphics processor (GPU) has evolved into an appealing choice for high performance computing due to its superior memory bandwidth, raw processing power, and flexible programm...
Kyle Spafford, Jeremy S. Meredith, Jeffrey S. Vett...
CLUSTER
2009
IEEE
15 years 10 months ago
Power-aware scheduling of virtual machines in DVFS-enabled clusters
—With the advent of Cloud computing, large-scale virtualized compute and data centers are becoming common in the computing industry. These distributed systems leverage commodity ...
Gregor von Laszewski, Lizhe Wang, Andrew J. Younge...