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141
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HPCA
2009
IEEE
16 years 4 months ago
Optimizing communication and capacity in a 3D stacked reconfigurable cache hierarchy
Cache hierarchies in future many-core processors are expected to grow in size and contribute a large fraction of overall processor power and performance. In this paper, we postula...
Niti Madan, Li Zhao, Naveen Muralimanohar, Anirudd...
144
Voted
HPCA
2003
IEEE
16 years 4 months ago
Power-Aware Control Speculation through Selective Throttling
With the constant advances in technology that lead to the increasing of the transistor count and processor frequency, power dissipation is becoming one of the major issues in high...
Juan L. Aragón, José González...
HPCA
2003
IEEE
16 years 4 months ago
Hierarchical Backoff Locks for Nonuniform Communication Architectures
This paper identifies node affinity as an important property for scalable general-purpose locks. Nonuniform communication architectures (NUCAs), for example CCNUMAs built from a f...
Zoran Radovic, Erik Hagersten
119
Voted
NOSSDAV
2009
Springer
15 years 10 months ago
Adaptive overlay topology for mesh-based P2P-TV systems
In this paper, we propose a simple and fully distributed mechanism for constructing and maintaining the overlay topology in mesh-based P2P-TV systems. Our algorithm optimizes the ...
Richard John Lobb, Ana Paula Couto da Silva, Emili...
132
Voted
ICPADS
2006
IEEE
15 years 9 months ago
Loop Scheduling with Complete Memory Latency Hiding on Multi-core Architecture
The widening gap between processor and memory performance is the main bottleneck for modern computer systems to achieve high processor utilization. In this paper, we propose a new...
Chun Xue, Zili Shao, Meilin Liu, Mei Kang Qiu, Edw...