41 search results - page 7 / 9 » DLL-conscious instruction fetch optimization for SMT process... |
ICCD
1999
IEEE
13 years 10 months ago
1999
IEEE
This paper describes a core-customization process of a CISC processor core for a given application program. It aims at the power reduction in the CISC processor core by fully util...
ICPP
2008
IEEE
14 years 21 days ago
2008
IEEE
The issue queue (IQ) is a key microarchitecture structure for exploiting instruction-level and thread-level parallelism in dynamically scheduled simultaneous multithreaded (SMT) p...
MICRO
1997
IEEE
13 years 10 months ago
1997
IEEE
Compiler optimizations are often driven by specific assumptions about the underlying architecture and implementation of the target machine. For example, when targeting shared-mem...
ASAP
2006
IEEE
13 years 10 months ago
2006
IEEE
State-of-the-art communication standards make extensive use of Turbo codes. The complex and power consuming designs that currently implement the turbo decoder expose the need for ...
CASES
2006
ACM
14 years 7 days ago
2006
ACM
In this paper, we propose a fully automatic dynamic scratchpad memory (SPM) management technique for instructions. Our technique loads required code segments into the SPM on deman...