7 search results - page 2 / 2 » DPPC: Dynamic power partitioning and capping in chip multipr... |
ICS
2005
Tsinghua U.
13 years 11 months ago
2005
Tsinghua U.
We propose an organization for the on-chip memory system of a chip multiprocessor, in which 16 processors share a 16MB pool of 256 L2 cache banks. The L2 cache is organized as a n...
HPCA
2011
IEEE
12 years 10 months ago
2011
IEEE
The number of cores in a single chip multiprocessor is expected to grow in coming years. Likewise, aggregate on-chip cache capacity is increasing fast and its effective utilizatio...