1536 search results - page 290 / 308 » DPS - Dynamic Parallel Schedules |
ICPP
2002
IEEE
15 years 2 months ago
2002
IEEE
Code size expansion of software-pipelined loops is a critical problem for DSP systems with strict code size constraint. Some ad-hoc code size reduction techniques were used to try...
INFOCOM
2002
IEEE
15 years 2 months ago
2002
IEEE
- This paper describes new optical switching architectures supporting asynchronous variable-length packets. Output line contention is resolved by optical delay line buffers. By int...
81
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EUROPAR
2009
Springer
15 years 2 months ago
2009
Springer
This paper addresses the issue of how to meet the strict timing constraints of (soft) real-time virtualized applications while the Virtual Machine (VM) hosting them is undergoing a...
107
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EUROMICRO
1999
IEEE
15 years 1 months ago
1999
IEEE
Software synthesis for system level design languages becomes feasible because the current technology, pricing and application trends will most likely alleviate the industrial empha...
MICRO
1996
IEEE
15 years 1 months ago
1996
IEEE
A machine description facility allows compiler writers to specify machine execution constraints to the optimization and scheduling phases of an instruction-level parallelism (ILP)...