1536 search results - page 301 / 308 » DPS - Dynamic Parallel Schedules |
IPPS
2010
IEEE
14 years 7 months ago
2010
IEEE
We consider the problem of broadcasting a large message in a large scale distributed platform. The message must be sent from a source node, with the help of the receiving peers whi...
86
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DAC
2002
ACM
15 years 10 months ago
2002
ACM
The design of high-throughput large-state Viterbi decoders relies on the use of multiple arithmetic units. The global communication channels among these parallel processors often ...
104
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DAC
2005
ACM
15 years 10 months ago
2005
ACM
The challenge of verifying a modern microprocessor design is an overwhelming one: Increasingly complex micro-architectures combined with heavy time-to-market pressure have forced ...
HPCA
2009
IEEE
15 years 10 months ago
2009
IEEE
The number of functional errors escaping design verification and being released into final silicon is growing, due to the increasing complexity and shrinking production schedules ...
HPCA
2009
IEEE
15 years 10 months ago
2009
IEEE
Heterogeneous multicores, such as Cell BE processors and GPGPUs, typically do not have caches for their accelerator cores because coherence traffic, cache misses, and latencies fr...