We propose an organization for the on-chip memory system of a chip multiprocessor, in which 16 processors share a 16MB pool of 256 L2 cache banks. The L2 cache is organized as a n...
Jaehyuk Huh, Changkyu Kim, Hazim Shafi, Lixin Zhan...
In this paper, we discuss a library generator for parallel sorting routines that examines the input characteristics (and the parameters they affect) to select the best performing ...
Brian A. Garber, Daniel Hoeflinger, Xiaoming Li, M...
Abstract— This paper presents a study of our proposed architecture for the setup of a MultiPoint-to-MultiPoint (MP2MP) Label Switched Path (LSP). This form of LSP is needed for e...
Ashraf Matrawy, Wei Yi, Ioannis Lambadaris, Chung-...
Distributed Inter-Process Communication (DIPC) provides the programmers of the Linux operating system with distributed programming facilities, including Distributed Shared Memory ...
We show empirically that some of the issues that affected the design of linear algebra libraries for distributed memory architectures will also likely affect such libraries for s...
Bryan Marker, Field G. Van Zee, Kazushige Goto, Gr...