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MICRO
1991
IEEE
126views Hardware» more  MICRO 1991»
15 years 1 months ago
Data Access Microarchitectures for Superscalar Processors with Compiler-Assisted Data Prefetching
The performance of superscalar processors is more sensitive to the memory system delay than their single-issue predecessors. This paper examines alternative data access microarchi...
William Y. Chen, Scott A. Mahlke, Pohua P. Chang, ...
MICRO
2003
IEEE
116views Hardware» more  MICRO 2003»
15 years 2 months ago
Universal Mechanisms for Data-Parallel Architectures
Data-parallel programs are both growing in importance and increasing in diversity, resulting in specialized processors targeted at specific classes of these programs. This paper ...
Karthikeyan Sankaralingam, Stephen W. Keckler, Wil...
CF
2011
ACM
13 years 9 months ago
SIFT: a low-overhead dynamic information flow tracking architecture for SMT processors
Dynamic Information Flow Tracking (DIFT) is a powerful technique that can protect unmodified binaries from a broad range of vulnerabilities such as buffer overflow and code inj...
Meltem Ozsoy, Dmitry Ponomarev, Nael B. Abu-Ghazal...
ISCA
2002
IEEE
104views Hardware» more  ISCA 2002»
14 years 9 months ago
Speculative Dynamic Vectorization
Traditional vector architectures have shown to be very effective for regular codes where the compiler can detect data-level parallelism. However, this SIMD parallelism is also pre...
Alex Pajuelo, Antonio González, Mateo Valer...
ICCD
2005
IEEE
114views Hardware» more  ICCD 2005»
15 years 6 months ago
Memory Bank Predictors
Cache memories are commonly implemented through multiple memory banks to improve bandwidth and latency. The early knowledge of the data cache bank that an instruction will access ...
Stefan Bieschewski, Joan-Manuel Parcerisa, Antonio...