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» Data Criticality in Network-On-Chip Design
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INFOCOM
2009
IEEE
15 years 4 months ago
Time Valid One-Time Signature for Time-Critical Multicast Data Authentication
Abstract—It is challenging to provide authentication to timecritical multicast data, where low end-to-end delay is of crucial importance. Consequently, it requires not only effi...
Qiyan Wang, Himanshu Khurana, Ying Huang, Klara Na...
87
Voted
DSN
2011
IEEE
13 years 10 months ago
Cross-layer resilience using wearout aware design flow
—As process technology shrinks devices, circuits experience accelerated wearout. Monitoring wearout will be critical for improving the efficiency of error detection and correctio...
Bardia Zandian, Murali Annavaram
92
Voted
VLSISP
2008
147views more  VLSISP 2008»
14 years 8 months ago
Data Reuse Exploration for Low Power Motion Estimation Architecture Design in H.264 Encoder
Data access usually leads to more than 50% of the power cost in a modern signal processing system. To realize a low-power design, how to reduce the memory access power is a critica...
Yu-Han Chen, Tung-Chien Chen, Chuan-Yung Tsai, Sun...
84
Voted
DATE
2009
IEEE
88views Hardware» more  DATE 2009»
15 years 5 months ago
Latency criticality aware on-chip communication
—Packet-switched interconnect fabric is a promising on-chip communication solution for many-core architectures. It offers high throughput and excellent scalability for on-chip da...
Zheng Li, Jie Wu, Li Shang, Robert P. Dick, Yihe S...
102
Voted
CSFW
2011
IEEE
13 years 10 months ago
Modular Protections against Non-control Data Attacks
—This paper introduces YARRA, a conservative extension to C to protect applications from non-control data attacks. YARRA programmers specify their data integrity requirements by ...
Cole Schlesinger, Karthik Pattabiraman, Nikhil Swa...