Sciweavers

635 search results - page 42 / 127
» Data Criticality in Network-On-Chip Design
Sort
View
ICML
1995
IEEE
16 years 1 months ago
Visualizing High-Dimensional Structure with the Incremental Grid Growing Neural Network
Understanding high-dimensional real world data usually requires learning the structure of the data space. The structure maycontain high-dimensional clusters that are related in co...
Justine Blackmore, Risto Miikkulainen
GECCO
2007
Springer
163views Optimization» more  GECCO 2007»
15 years 6 months ago
Discovering event evidence amid massive, dynamic datasets
Automated event extraction remains a very difficult challenge requiring information analysts to manually identify key events of interest within massive, dynamic data. Many techniq...
Robert M. Patton, Thomas E. Potok
IMC
2010
ACM
14 years 10 months ago
What happened in my network: mining network events from router syslogs
Router syslogs are messages that a router logs to describe a wide range of events observed by it. They are considered one of the most valuable data sources for monitoring network ...
Tongqing Qiu, Zihui Ge, Dan Pei, Jia Wang, Jun Xu
87
Voted
CSREAESA
2004
15 years 1 months ago
A High Performance, Low Area Overhead Carry Lookahead Adder
Adders are some of the most critical data path circuits requiring considerable design effort in order to "squeeze" out as much performance gain as possible. Many adder d...
James Levy, Jabulani Nyathi
ICCD
2001
IEEE
90views Hardware» more  ICCD 2001»
15 years 9 months ago
Interconnect-centric Array Architectures for Minimum SRAM Access Time
‡ Physical and generic models that analytically couple the array architecture of CMOS SRAMs with the wire lengths and fan-outs along critical paths to decode and sense data are r...
Azeez J. Bhavnagarwala, Stephen V. Kosonocky, Jame...