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» Data Criticality in Network-On-Chip Design
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136
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DAC
2004
ACM
15 years 4 months ago
Communication-efficient hardware acceleration for fast functional simulation
This paper presents new technology that accelerates system verification. Traditional methods for verifying functional designs are based on logic simulation, which becomes more tim...
Young-Il Kim, Woo-Seung Yang, Young-Su Kwon, Chong...
ISLPED
2007
ACM
96views Hardware» more  ISLPED 2007»
15 years 2 months ago
Low-power process-variation tolerant arithmetic units using input-based elastic clocking
In this paper we propose a design methodology for low-power, high-performance, process-variation tolerant architecture for arithmetic units. The novelty of our approach lies in th...
Debabrata Mohapatra, Georgios Karakonstantis, Kaus...
TON
2008
125views more  TON 2008»
15 years 13 days ago
Two techniques for fast computation of constrained shortest paths
Abstract-- Computing constrained shortest paths is fundamental to some important network functions such as QoS routing, which is to find the cheapest path that satisfies certain co...
Shigang Chen, Meongchul Song, Sartaj Sahni
118
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TPDS
2010
174views more  TPDS 2010»
14 years 11 months ago
Parallel Two-Sided Matrix Reduction to Band Bidiagonal Form on Multicore Architectures
The objective of this paper is to extend, in the context of multicore architectures, the concepts of tile algorithms [Buttari et al., 2007] for Cholesky, LU, QR factorizations to t...
Hatem Ltaief, Jakub Kurzak, Jack Dongarra
125
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WINET
2010
224views more  WINET 2010»
14 years 11 months ago
Hierarchical geographic multicast routing for wireless sensor networks
Wireless sensor networks comprise typically dense deployments of large networks of small wireless capable sensor devices. In such networks, multicast is a fundamental routing servi...
Dimitrios Koutsonikolas, Saumitra M. Das, Y. Charl...