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ICCAD
2006
IEEE
131views Hardware» more  ICCAD 2006»
15 years 6 months ago
High-level synthesis challenges and solutions for a dynamically reconfigurable processor
A dynamically reconfigurable processor (DRP) is designed to achieve high area efficiency by switching reconfigurable data paths dynamically. Our DRP architecture has a stand alone...
Takao Toi, Noritsugu Nakamura, Yoshinosuke Kato, T...
VISUALIZATION
1998
IEEE
15 years 1 months ago
Large scale terrain visualization using the restricted quadtree triangulation
Real-time rendering of triangulated surfaces has attracted growing interest in the last few years. However, interactive visualization of very large scale grid digital elevation mo...
Renato Pajarola
CN
1998
100views more  CN 1998»
14 years 9 months ago
Metabroker: A Generic Broker for Electronic Commerce
In traditional commerce, brokers act as middlemen between customers and providers, aggregating, repackaging and adding value to products, services or information. In the broadest ...
Steve J. Caughey, David B. Ingham, Paul Watson
SIGMOD
2009
ACM
192views Database» more  SIGMOD 2009»
15 years 9 months ago
A gauss function based approach for unbalanced ontology matching
Ontology matching, aiming to obtain semantic correspondences between two ontologies, has played a key role in data exchange, data integration and metadata management. Among numero...
Qian Zhong, Hanyu Li, Juanzi Li, Guo Tong Xie, Jie...
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JSA
2010
158views more  JSA 2010»
14 years 4 months ago
Scalable mpNoC for massively parallel systems - Design and implementation on FPGA
The high chip-level integration enables the implementation of large-scale parallel processing architectures with 64 and more processing nodes on a single chip or on an FPGA device...
Mouna Baklouti, Yassine Aydi, Philippe Marquet, Je...