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MICRO
2002
IEEE
117views Hardware» more  MICRO 2002»
14 years 9 months ago
Drowsy instruction caches: leakage power reduction using dynamic voltage scaling and cache sub-bank prediction
On-chip caches represent a sizeable fraction of the total power consumption of microprocessors. Although large caches can significantly improve performance, they have the potentia...
Nam Sung Kim, Krisztián Flautner, David Bla...
ASPLOS
2004
ACM
15 years 3 months ago
HIDE: an infrastructure for efficiently protecting information leakage on the address bus
+ XOM-based secure processor has recently been introduced as a mechanism to provide copy and tamper resistant execution. XOM provides support for encryption/decryption and integrit...
Xiaotong Zhuang, Tao Zhang, Santosh Pande
VLSID
2006
IEEE
169views VLSI» more  VLSID 2006»
15 years 3 months ago
A Low Leakage and SNM Free SRAM Cell Design in Deep Sub Micron CMOS Technology
As the IC process technology scales, the oxide thickness and operating voltage continues to decrease. The gate oxide thickness in recent and future IC process technology has appro...
Sanjeev K. Jain, Pankaj Agarwal
ICASSP
2011
IEEE
14 years 1 months ago
A wavenumber-fitting extrapolation method for FFT-based near-field acoustic holography using microphone array
Near-field acoustic holography (NAH) is an important acoustic visualization technique which can be implemented efficiently through the fast Fourier transform (FFT). However, whe...
Benxu Liu, Bremananth Ramachandran, Andy W. H. Kho...
VLSID
2006
IEEE
129views VLSI» more  VLSID 2006»
15 years 10 months ago
Modeling and Reduction of Gate Leakage during Behavioral Synthesis of NanoCMOS Circuits
For a nanoCMOS of sub-65nm technology, where the gate oxide (SiO2) thickness is very low, the gate leakage is one of the major components of power dissipation. In this paper, we pr...
Saraju P. Mohanty, Elias Kougianos