We present an error-tolerant SRAM design optimized for ultra-low standby power. Using SRAM cell optimization techniques, the maximum data retention voltage (DRV) of a 90nm 26kb SR...
First-in first-out (FIFO) memories are widely used in SoC for data buffering and flow control. In this paper, a robust ultra-low power asynchronous FIFO memory is proposed. With s...
Increased leakage and process variations make distinction between fault-free and faulty chips by IDDQ test difficult. Earlier the concept of Current Ratios (CR) was proposed to sc...
With more and more social network data being released, protecting the sensitive information within social networks from leakage has become an important concern of publishers. Adve...