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ICASSP
2008
IEEE
15 years 9 months ago
Address assignment sensitive variable partitioning and scheduling for DSPS with multiple memory banks
Multiple memory banks design is employed in many high performance DSP processors. This architectural feature supports higher memory bandwidth by allowing multiple data memory acce...
Chun Jason Xue, Tiantian Liu, Zili Shao, Jingtong ...
114
Voted
ISCA
1998
IEEE
151views Hardware» more  ISCA 1998»
15 years 7 months ago
Integrated Predicated and Speculative Execution in the IMPACT EPIC Architecture
Explicitly Parallel Instruction Computing (EPIC) architectures require the compiler to express program instruction level parallelism directly to the hardware. EPIC techniques whic...
David I. August, Daniel A. Connors, Scott A. Mahlk...
133
Voted
SCP
1998
112views more  SCP 1998»
15 years 2 months ago
Structured Gamma
The Gamma language is based on the chemical reaction metaphor which has a number of benefits with respect to parallelism and program derivation. But the original definition of G...
Pascal Fradet, Daniel Le Métayer
133
Voted
IPPS
2006
IEEE
15 years 8 months ago
Performance analysis of Java concurrent programming: a case study of video mining system
As multi/many core processors become prevalent, programming language is important in constructing efficient parallel applications. In this work, we build a multithreaded video min...
Wenlong Li, Eric Li, Ran Meng, Tao Wang, Carole Du...
126
Voted
IPPS
2003
IEEE
15 years 8 months ago
Accurate Method for Fast Design of Diagnostic Oligonucleotide Probe Sets for DNA Microarrays
We present a method for the automatic generation of oligonucleotide probe sets for DNA microarrays. This approach is well suited particularly for specificity evaluation of design...
Andreas Krause, Markus Kräutner, Harald Meier