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ICS
2001
Tsinghua U.
15 years 8 months ago
Reducing the complexity of the issue logic
The issue logic of dynamically scheduled superscalar processors is one of their most complex and power-consuming parts. In this paper we present alternative issue-logic designs th...
Ramon Canal, Antonio González
130
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IPPS
1998
IEEE
15 years 8 months ago
A Java Development and Runtime Environment for Reconfigurable Computing
Fast runtime reconfigurable hardware enables system designers to swap hardware into and out of an FPGA much as the pages of virtual memory are swapped into and out of virtual memor...
Don Davis, Michael Barr, Toby Bennett, Stephen Edw...
155
Voted
PVG
2003
IEEE
138views Visualization» more  PVG 2003»
15 years 9 months ago
Sort-First, Distributed Memory Parallel Visualization and Rendering
While commodity computing and graphics hardware has increased in capacity and dropped in cost, it is still quite difficult to make effective use of such systems for general-purpos...
E. Wes Bethel, Greg Humphreys, Brian E. Paul, J. D...
154
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BMCBI
2010
153views more  BMCBI 2010»
15 years 3 months ago
Pash 3.0: A versatile software package for read mapping and integrative analysis of genomic and epigenomic variation using massi
Background: Massively parallel sequencing readouts of epigenomic assays are enabling integrative genome-wide analyses of genomic and epigenomic variation. Pash 3.0 performs sequen...
Cristian Coarfa, Fuli Yu, Christopher A. Miller, Z...
157
Voted
ICS
2000
Tsinghua U.
15 years 7 months ago
Automatic loop transformations and parallelization for Java
From a software engineering perspective, the Java programming language provides an attractive platform for writing numerically intensive applications. A major drawback hampering i...
Pedro V. Artigas, Manish Gupta, Samuel P. Midkiff,...