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HIPEAC
2011
Springer
14 years 3 months ago
NoC-aware cache design for multithreaded execution on tiled chip multiprocessors
In chip multiprocessors (CMPs), data accesslatency dependson the memory hierarchy organization, the on-chip interconnect (NoC), and the running workload. Reducing data access late...
Ahmed Abousamra, Alex K. Jones, Rami G. Melhem
AMAST
2004
Springer
15 years 9 months ago
A Science of Software Design
concerns, abstraction (particularly hierarchical abstraction), simplicity, and restricted visibility (locality of information). The overall goal behind these principles was stated ...
Don S. Batory
SIGMETRICS
2010
ACM
206views Hardware» more  SIGMETRICS 2010»
15 years 9 months ago
Successive c-optimal designs: a scalable technique to optimize the measurements on large networks
We propose a new approach to optimize the deployment and the sampling rates of network monitoring tools, such as Netflow, on a large IP network. It reduces to solving a stochasti...
Guillaume Sagnol, Mustapha Bouhtou, Stephane Gaube...
DCC
2007
IEEE
16 years 3 months ago
Algorithms and Hardware Structures for Unobtrusive Real-Time Compression of Instruction and Data Address Traces
Instruction and data address traces are widely used by computer designers for quantitative evaluations of new architectures and workload characterization, as well as by software de...
Milena Milenkovic, Aleksandar Milenkovic, Martin B...
ASPLOS
2009
ACM
16 years 4 months ago
3D finite difference computation on GPUs using CUDA
In this paper we describe a GPU parallelization of the 3D finite difference computation using CUDA. Data access redundancy is used as the metric to determine the optimal implement...
Paulius Micikevicius