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IV
2005
IEEE
149views Visualization» more  IV 2005»
15 years 9 months ago
Visualisation Techniques for Users and Designers of Layout Algorithms
Visualisation systems consisting of a set of components through which data and interaction commands flow have been explored by a number of researchers. Such hybrid and multistage ...
Greg Ross, Alistair Morrison, Matthew Chalmers
FCCM
2008
IEEE
212views VLSI» more  FCCM 2008»
15 years 10 months ago
Map-reduce as a Programming Model for Custom Computing Machines
The map-reduce model requires users to express their problem in terms of a map function that processes single records in a stream, and a reduce function that merges all mapped out...
Jackson H. C. Yeung, C. C. Tsang, Kuen Hung Tsoi, ...
SBACPAD
2008
IEEE
170views Hardware» more  SBACPAD 2008»
15 years 10 months ago
Using Analytical Models to Efficiently Explore Hardware Transactional Memory and Multi-Core Co-Design
Transactional memory is emerging as a parallel programming paradigm for multi-core processors. Despite the recent interest in transactional memory, there has been no study to char...
James Poe, Chang-Burm Cho, Tao Li
ISESE
2005
IEEE
15 years 9 months ago
Empirical study design in the area of high-performance computing (HPC)
The development of High-Performance Computing (HPC) programs is crucial to progress in many fields of scientific endeavor. We have run initial studies of the productivity of HPC d...
Forrest Shull, Jeffrey Carver, Lorin Hochstein, Vi...
IWOMP
2007
Springer
15 years 10 months ago
Supporting OpenMP on Cell
The Cell processor is a heterogeneous multi-core processor with one Power Processing Engine (PPE) core and eight Synergistic Processing Engine (SPE) cores. Each SPE has a directly...
Kevin O'Brien, Kathryn M. O'Brien, Zehra Sura, Ton...