4198 search results - page 412 / 840 » Data Parallel Program Design |
161
Voted
CODES
2005
IEEE
15 years 10 months ago
2005
IEEE
Arbitrary memory dependencies and variable latency memory systems are major obstacles to the synthesis of large-scale ASIC systems in high-level synthesis. This paper presents SOM...
159
click to vote
IEEEPACT
2002
IEEE
15 years 10 months ago
2002
IEEE
Simultaneous Multithreading (SMT) processors achieve high processor throughput at the expense of single-thread performance. This paper investigates resource allocation policies fo...
147
Voted
ICDCS
2010
IEEE
15 years 9 months ago
2010
IEEE
—Wireless Sensor Network (WSN) applications are typically event-driven. While the source codes of these applications may look simple, they are executed with a complicated concurr...
177
click to vote
ICS
2010
Tsinghua U.
15 years 7 months ago
2010
Tsinghua U.
The growing influence of wire delay in cache design has meant that access latencies to last-level cache banks are no longer constant. Non-Uniform Cache Architectures (NUCAs) have ...
161
click to vote
BMCBI
2010
15 years 5 months ago
2010
Background: There is an increasing number of proteins with known structure but unknown function. Determining their function would have a significant impact on understanding diseas...