4198 search results - page 496 / 840 » Data Parallel Program Design |
124
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IEEEPACT
2006
IEEE
15 years 10 months ago
2006
IEEE
Modern out-of-order processors with non-blocking caches exploit Memory-Level Parallelism (MLP) by overlapping cache misses in a wide instruction window. The exploitation of MLP, h...
142
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UM
2009
Springer
15 years 11 months ago
2009
Springer
Abstract. Recent sensor technologies have enabled the capture of users’ behavior data. Given the large amount of data currently available from sensor-equipped environments, it is...
142
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CORR
1999
Springer
15 years 4 months ago
1999
Springer
Most debuggers are notoriously machine-dependent, but some recent research prototypes achieve varying degrees of machine-independence with novel designs. Cdb, a simple source-leve...
135
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ICS
2009
Tsinghua U.
15 years 11 months ago
2009
Tsinghua U.
The Cell BE is a multicore processor with eight vector accelerators (called SPEs) that implement explicit cache management through direct memory access engines. While the Cell has...
104
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ASAP
2007
IEEE
15 years 11 months ago
2007
IEEE
We present a memory efficient, practical, systolic, parallel architecture for the complete 0/1 knapsack dynamic programming problem, including backtracking. This problem was inte...