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ISCA
2010
IEEE
176views Hardware» more  ISCA 2010»
15 years 8 months ago
Forwardflow: a scalable core for power-constrained CMPs
Chip Multiprocessors (CMPs) are now commodity hardware, but commoditization of parallel software remains elusive. In the near term, the current trend of increased coreper-socket c...
Dan Gibson, David A. Wood
SPAA
1997
ACM
15 years 8 months ago
Pipelining with Futures
Pipelining has been used in the design of many PRAM algorithms to reduce their asymptotic running time. Paul, Vishkin, and Wagener (PVW) used the approach in a parallel implementat...
Guy E. Blelloch, Margaret Reid-Miller
91
Voted
ISCAS
2006
IEEE
114views Hardware» more  ISCAS 2006»
15 years 9 months ago
System for deposition and characterization of polypyrrole/gold bilayer hinges
— We report on a custom designed system for the deposition and characterization of polypyrrole bilayer actuators. Unlike conventional commercial electrochemical cells and potenti...
Edward Choi, Yingkai Liu, Elisabeth Smela, Andreas...
LCTRTS
2001
Springer
15 years 8 months ago
ILP-based Instruction Scheduling for IA-64
The IA-64 architecture has been designed as a synthesis of VLIW and superscalar design principles. It incorporates typical functionality known from embedded processors as multiply...
Daniel Kästner, Sebastian Winkel
ICDAR
2009
IEEE
15 years 1 months ago
PixLabeler: User Interface for Pixel-Level Labeling of Elements in Document Images
We present a user interface design for labeling elements in document images at a pixel level. Labels are represented by overlay color, which might map to such terms as "handw...
Eric Saund, Jing Lin, Prateek Sarkar