Background: The availability of complete genomic sequences for hundreds of organisms promises to make obtaining genome-wide estimates of substitution rates, selective constraints ...
Amy Egan, Anup Mahurkar, Jonathan Crabtree, Jonath...
SARC merges cache controller and network interface functions by relying on a single hardware primitive: each access checks the tag and the state of the addressed line for possible...
Streamlining communication is key to achieving good performance in shared-memory parallel programs. While full hardware support for cache coherence generally offers the best perfo...
Performance evaluation is a central issue in the design of complex real-time systems. In this work, we propose an extension of socalled "Max-Plus" algebraic techniques to...
As the number of cores and threads in manycore compute accelerators such as Graphics Processing Units (GPU) increases, so does the importance of on-chip interconnection network des...