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TVLSI
2010
14 years 4 months ago
C-Pack: A High-Performance Microprocessor Cache Compression Algorithm
Microprocessor designers have been torn between tight constraints on the amount of on-chip cache memory and the high latency of off-chip memory, such as dynamic random access memor...
Xi Chen, Lei Yang, Robert P. Dick, Li Shang, Haris...
CF
2009
ACM
15 years 4 months ago
Core monitors: monitoring performance in multicore processors
As we reach the limits of single-core computing, we are promised more and more cores in our systems. Modern architectures include many performance counters per core, but few or no...
Paul E. West, Yuval Peress, Gary S. Tyson, Sally A...
MICRO
2006
IEEE
145views Hardware» more  MICRO 2006»
15 years 4 months ago
Virtually Pipelined Network Memory
We introduce virtually-pipelined memory, an architectural technique that efficiently supports high-bandwidth, uniform latency memory accesses, and high-confidence throughput eve...
Banit Agrawal, Timothy Sherwood
89
Voted
IMC
2006
ACM
15 years 4 months ago
Measurement based analysis, modeling, and synthesis of the internet delay space
Understanding the characteristics of the Internet delay space (i.e., the all-pairs set of static round-trip propagation delays among edge networks in the Internet) is important fo...
Bo Zhang, T. S. Eugene Ng, Animesh Nandi, Rudolf H...
82
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OOPSLA
2005
Springer
15 years 3 months ago
MDAbench: a tool for customized benchmark generation using MDA
Designing component-based application that meets performance requirements remains a challenging problem, and usually requires a prototype to be constructed to benchmark performanc...
Liming Zhu, Yan Liu, Ian Gorton, Ngoc Bao Bui