213 search results - page 25 / 43 » Data Speculative Multithreaded Architecture |
DAC
2001
ACM
16 years 21 days ago
2001
ACM
In order to meet the high throughput requirements of applications exhibiting high ILP, VLIW ASIPs may increasingly include large numbers of functional unitsFUs. Unfortunately, `sw...
90
Voted
ASPDAC
2009
ACM
15 years 3 months ago
2009
ACM
Abstract-- The increasing wire delay constraints in deep submicron VLSI designs have led to the emergence of scalable and modular Network-on-Chip (NoC) architectures. As the power ...
ICPP
2009
IEEE
15 years 6 months ago
2009
IEEE
Memory-intensive threads can hoard shared resources without making progress on a multithreading processor (SMT), thereby hindering the overall system performance. A recent promisi...
EUROPAR
2010
Springer
15 years 25 days ago
2010
Springer
Abstract. Shared last level cache is crucial to performance. However, multithread program model incurs serious contention in shared cache. In this paper, to reduce average cache ac...
123
Voted
MICRO
2010
IEEE
14 years 10 months ago
2010
IEEE
This paper presents a task-centric memory model for 1000-core compute accelerators. Visual computing applications are emerging as an important class of workloads that can exploit ...