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CODES
2008
IEEE
15 years 8 months ago
Speculative DMA for architecturally visible storage in instruction set extensions
Instruction set extensions (ISEs) can accelerate embedded processor performance. Many algorithms for ISE generation have shown good potential; some of them have recently been expa...
Theo Kluter, Philip Brisk, Paolo Ienne, Edoardo Ch...
EIT
2008
IEEE
15 years 8 months ago
Taming XML: Objects first, then markup
Abstract—Processing markup in object-oriented languages often requires the programmer to focus on the objects generating the markup rather than the more pertinent domain objects....
Matt Bone, Peter F. Nabicht, Konstantin Läufe...
RTSS
2008
IEEE
15 years 7 months ago
Predictable Interrupt Management and Scheduling in the Composite Component-Based System
This paper presents the design of user-level scheduling hierarchies in the Composite component-based system. The motivation for this is centered around the design of a system that...
Gabriel Parmer, Richard West
MICRO
2007
IEEE
129views Hardware» more  MICRO 2007»
15 years 7 months ago
A Framework for Coarse-Grain Optimizations in the On-Chip Memory Hierarchy
Current on-chip block-centric memory hierarchies exploit access patterns at the fine-grain scale of small blocks. Several recently proposed techniques for coherence traffic reduct...
Jason Zebchuk, Elham Safi, Andreas Moshovos
EMSOFT
2007
Springer
15 years 7 months ago
Exploiting non-volatile RAM to enhance flash file system performance
Non-volatile RAM (NVRAM) such as PRAM (Phase-change RAM), FeRAM (Ferroelectric RAM), and MRAM (Magnetoresistive RAM) has characteristics of both non-volatile storage and random ac...
In Hwan Doh, Jongmoo Choi, Donghee Lee, Sam H. Noh