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84
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ISCA
2010
IEEE
199views Hardware» more  ISCA 2010»
15 years 2 months ago
A case for FAME: FPGA architecture model execution
Given the multicore microprocessor revolution, we argue that the architecture research community needs a dramatic increase in simulation capacity. We believe FPGA Architecture Mod...
Zhangxi Tan, Andrew Waterman, Henry Cook, Sarah Bi...
ANSOFT
1998
157views more  ANSOFT 1998»
14 years 9 months ago
Software Engineering Programmes are not Computer Science Programmes
Programmes in “Software Engineering” have become a source of contention in many universities. Computer Science departments, many of which have used that phrase to describe ind...
David Lorge Parnas
123
Voted
VLSID
2007
IEEE
231views VLSI» more  VLSID 2007»
15 years 10 months ago
AHIR: A Hardware Intermediate Representation for Hardware Generation from High-level Programs
We present AHIR, an intermediate representation (IR), that acts as a transition layer between software compilation and hardware synthesis. Such a transition layer is intended to t...
Sameer D. Sahasrabuddhe, Hakim Raja, Kavi Arya, Ma...
79
Voted
LCPC
2000
Springer
15 years 1 months ago
Efficient Dynamic Local Enumeration for HPF
In translating HPF programs, a compiler has to generate local iteration and communication sets. Apart from local enumeration, local storage compression is an issue, because in HPF ...
Will Denissen, Henk J. Sips
95
Voted
EDBT
2008
ACM
146views Database» more  EDBT 2008»
14 years 11 months ago
SPARQLing constraints for RDF
The goal of the Semantic Web is to support semantic interoperability between applications exchanging data on the web. The idea heavily relies on data being made available in machi...
Georg Lausen, Michael Meier 0002, Michael Schmidt